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1 compact synchronous buck regulators isl8025, isl8025a the isl8025, isl8025a are high ly efficient, monolithic, synchronous step-down dc/dc conver ters that can deliver 5a of continuous output current from a 2.7v to 5.5v input supply. the devices use current mode control architecture to deliver a very low duty cycle operation at high frequency with fast transient response and excellent loop stability. the isl8025, isl8025a integrates a very low on-resistance p-channel (45m ? ) high-side fet and n-channel (19m ? ) low-side fet to maximize efficiency and minimize external component count. the 100% duty-cycle operation allows less than 225mv dropout voltage at 5a output current. the operation frequency of the pulse-width modulator (pwm) is adjustable from 500khz to 4mhz. the default switching frequency, which is set by conne cting the fs pin high, is 1mhz for the isl8025 and 2mhz for the isl8025a. the isl8025, isl8025a can be co nfigured for discontinuous or forced continuous op eration at light load . forced continuous operation reduces noise and rf interference, while discontinuous mode provides higher efficiency by reducing switching losses at light loads. fault protection is provided by internal hiccup mode current limiting during short circuit an d overcurrent conditions. other protection, such as overvoltage and over-temperature, are also integrated into the device. a power-good output voltage monitor indicates when the output is in regulation. the isl8025, isl8025a offers a 1ms power-good (pg) timer at power-up. when in shutdo wn, the isl8025, isl8025a discharges the output capacitor through an internal soft-stop switch. other features include internal fixed or adjustable soft-start and internal/external compensation. the isl8025, isl8025a are offered in a space saving 16 ld 3x3 pb-free qfn package with an exposed pad for improved thermal performance and 1mm maximum height. the complete converter occupies less than 0.22 in 2 area. features ? 2.7v to 5.5v input voltage range ? very low on-resistance fet?s - p-channel 45m ? and n-channel 19m ? typical values ? high efficiency synchronous buck regulator with up to 95% efficiency ? pin-to-pin compatible with isl8023 and isl8024 ? 0.8% reference accuracy over-temperature/load/line ? complete bom with as few as 3 external parts ? internal soft-start: 1ms or adjustable ? soft-stop output discharge during disable ? adjustable frequency from 500khz to 4mhz - default at 1mhz (isl8025), 2mhz (isl8025a) ? external synchronization up to 4mhz ? over-temperature, overcurrent, overvoltage and negative overcurrent protection applications ? dc/dc pol modules ? c/p, fpga and dsp power ? plug-in dc/dc modules for routers and switchers ?portable instruments ? test and measurement systems ? li-ion battery powered devices related literature ? see an1806 , ?5a low quiescent current high efficiency synchronous buck regulator? figure 1. typical application circuit configuration (internal compensation option) figure 2. efficiency vs load f sw = 1mhz, v in = 5v, mode = pfm, t a = +25c vin vdd pg sync pgnd fb pgnd sgnd 1 3 2 4 12 10 11 9 vout c1 2 x 22f 22pf c3* +0.6v gnd vin gnd en isl8025, isl8025a pad 17 +2.7v ?+5.5v +1.8v/5a en 5 fs 6 ss 7 comp 8 16 15 14 13 vin phase phase phase r1 100k pg 100k r3 r2 200k l1 1.0h 2 x 22f c2 *c3 is optional. it is recommended to put a placeholder for it and check loop analysis before use. r 2 r 3 v o vfb ------------ 1 ? ?? ?? = (eq. 1) 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) efficiency (%) 1.2v out 1.5v out 1.8v out 2.5v out 3.3v out february 20, 2013 fn8357.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl8025, isl8025a 2 fn8357.0 february 20, 2013 table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical operating performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 typical operating performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pwm control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 frequency adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 negative current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 pg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 uvlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 soft start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 discharge mode (soft-stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power mosfets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 thermal shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 output inductor and capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 loop compensation design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 pcb layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
isl8025, isl8025a 3 fn8357.0 february 20, 2013 pin configuration isl8025, isl8025a (16 ld tqfn) top view 1 3 4 vin vdd sync vin phase phase comp 2 7 5 6 fb pgnd en fs pg ss 8 11 9 10 16 13 15 14 12 sgnd pgnd phase vin pad pin descriptions pin number symbol description 1, 16 vin input supply voltage. place a minimum of two 22 f ceramic capacitors from vin to pgnd as close as possible to the ic for decoupling. 2 vdd input supply voltage for the logic. connect vin pin. 3 pg power-good is an open-drain output. use a 10k ? to 100k ? pull-up resistor connected between vin and pg. at power-up or en hi , pg rising edge is delayed by 1ms up on output reached within regulation. 4 sync mode selection pin. connect to logic high or inpu t voltage vin for pwm mode. connect to logic low or ground for pfm mode. connect to an external function generator for synchronization with the positive edge trigger. there is an internal 1m ? pull-down resistor to prevent an undefined logic state in case of sync pin float. 5 en regulator enable pin. enable the output when driven to high. shutdown the chip and discharge output capacitor when driven to low. 6 fs this pin sets the oscillator switching frequency, using a resistor, rfs, from the fs pin to gnd. the frequency of operation may be programmed between 500khz to 4mhz. the default frequency is 1mhz if fs is connected to vin. 7 ss ss is used to adjust the soft-start time. set to sg nd for internal 1ms rise time. connect a capacitor from ss to sgnd to adjust the soft-start time. do not use more than 33nf per ic. 8, 9 comp, fb the feedback network of the regulator, fb , is the negative input to the transconductance error amplifier. comp is the output of the amplifier if comp is not tied to vdd. otherwise, comp is disconnected thru a mosfet for internal compen sation. must connect comp to vdd in internal compensation mode. the output voltage is set by an external resistor divider connected to fb. with a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6v reference. there is an internal compensation to meet a typical application. additional external networks across comp and sgnd might be required to improve the loop compensation of the amplifier operation. in addition, the regulator power-good and undervol tage protection circuitry use fb to monitor the regulator output voltage. 10 sgnd signal ground. 11, 12 pgnd power ground. 13, 14, 15 phase switching node connections. connect to one te rminal of the inductor. this pin is discharged by a 100 resistor when the device is disabled. see?functional block diagram? on page 5 for more detail. exposed pad - the exposed pad must be connected to the sg nd pin for proper electrical performance. place as many vias as possible under the pad connecting to sgnd plane for optimal thermal performance.
isl8025, isl8025a 4 fn8357.0 february 20, 2013 ordering information part number (notes 1, 2, 3) part marking operation frequency (mhz) temp. range (c) package (pb-free) pkg. dwg. # isl8025irtajz 025a 1 -40 to +85 16 ld 3x3 tqfn l16.3x3d ISL8025AIRTAJZ 25aa 2 -40 to +85 16 ld 3x3 tqfn l16.3x3d notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl8025 , isl8025a . for more information on msl please see techbrief tb363 . table 1. summary of key differences part number i out (max) (a) f sw range (mhz) v in range (v) v out range (v) part size (mm) isl8025 5 programmable 0.5mhz to 4mhz 2.7 to 5.5 0.6 to 5.5 3x3 isl8025a programmable 1mhz to 4mhz notes: 4. the evaluation kit default configuration is v out = 1.8v, f sw =1mhz. 5. v ref is 0.6v. table 2. isl8025 component selection v out 0.8v 1.2v 1.5v 1.8v 2.5v 3.3v 3.6v c1 2 x 22f 2 x 22f 2 x 22f 2 x 22f 2 x 22f 2 x 22f 2 x 22f c2 4 x 22f 2 x 22f 2 x 22f 2 x 22f 2 x 22f 2 x 22f 2 x 22f c3 22pf 22pf 22pf 22pf 22pf 22pf 22pf l1 0.47~1h 0.47~1h 0.47~1h 0.68~1.5h 0.68~1.5h 1~2.2h 1~2.2h r2 33k 100k 150k 200k 316k 450k 500k r3 100k 100k 100k 100k 100k 100k 100k table 3. isl8025a component selection v out 0.8v 1.2v 1.5v 1.8v 2.5v 3.3v 3.6v c1 22f 22f 22f 22f 22f 22f 22f c2 3 x 22f 2 x 22f 2 x 22f 2 x 22f 2 x 22f 2 x 22f 2 x 22f c3 22pf 22pf 22pf 22pf 22pf 22pf 22pf l1 0.22~0.47h 0.22~0.47h 0.22~0.47h 0.33~0.68h 0.33~0.68h 0.47~1h 0.47~1h r2 33k 100k 150k 200k 316k 450k 500k r3 100k 100k 100k 100k 100k 100k 100k
isl8025, isl8025a 5 fn8357.0 february 20, 2013 figure 3. functional block diagram phase + + csa + + ocp skip + + + slope comp slope soft start soft- eamp comp pwm/pfm logic controller protection hs driver fb + 0.85*vref pg sync shutdown vin pgnd oscillator zero-cross sensing bandgap scp + 0.5v en shutdown 1ms delay 55pf 100k sgnd 3pf 6k - - - - - - - vdd comp 100 shutdown ls driver fs iset threshold vref + neg current sensing p n + 0.8v - uv ov ss
isl8025, isl8025a 6 fn8357.0 february 20, 2013 absolute maximum ratings (reference to gnd) thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.8v (dc) or 7v (20ms) en, fs, pg, sync, vfb . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v phase . . . . . . . . . . . . -1.5v (100ns)/-0.3v (dc) to 6.5v (dc) or 7v (20ms) comp, ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v esd ratings human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . . . 3kv charged device model (tested per jesd22-c101e). . . . . . . . . . . . . . 2kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . . 300v latch up (tested per jesd-78a; class 2, level a) . . . . . .100ma @ +85c thermal resistance ja (c/w) jc (c/w) 16 ld tqfn package (notes 6, 7) . . . . . . . 47 6.5 junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 5a ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 7. jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, all parameter limits are esta blished over the recommended operating conditions and the typical specification are measured at the following conditions: t a = -40c to +85c, v in = 3.6v, en = v in , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 8) typ max (note 8) units input supply v in undervoltage lockout threshold v uvlo rising, no load 2.5 2.7 v falling, no load 2.2 2.4 v quiescent supply current i vin sync = gnd, no load at the output 50 a sync = gnd, no load at the output and no switches switching 50 60 a sync = v in , f sw = 1mhz, no load at the output 8 15 ma sync = v in , f sw = 2mhz, no load at the output 16 23 ma shutdown supply current i sd sync = gnd, v in = 5.5v, en = low 5 7 a output regulation reference voltage v ref 0.595 0.600 0.605 v vfb bias current i vfb vfb = 0.75v 0.1 a line regulation v in = v o + 0.5v to 5.5v (minimal 2.7v) 0.2 %/v soft-start ramp time cycle ss = sgnd 1 ms soft-start charging current i ss v ss = 0.1v 1.45 1.85 2.25 a overcurrent protection current limit blanking time t ocon 17 clock pulses overcurrent and auto restart period t ocoff 8 ss cycle positive peak current limit i plimit 5a application 6 7.5 9 a peak skip limit i skip 5a application (see ?application information? on page 18 for more detail) 0.8 1 1.2 a zero cross threshold -200 200 ma
isl8025, isl8025a 7 fn8357.0 february 20, 2013 negative current limit i nlimit -4.5 -3 -1.5 a compensation error amplifier trans-conductance f sw = v in 60 a/v f sw with resistor 120 a/v trans-resistance rt 5a application (test at 3.6v) 0.155 0.175 0.195 ? phase p-channel mosfet on-resistance v in = 5v, i o = 200ma 45 55 m ? v in = 2.7v, i o = 200ma 70 90 m ? n-channel mosfet on-resistance v in = 5v, i o = 200ma 19 25 m ? v in = 2.7v, i o = 200ma 28 37 m ? phase maximum duty cycle 100 % phase minimum on-time sync = high 140 ns oscillator nominal switching frequency f sw f sw = v in , isl8025 800 1000 1200 khz f sw = v in , isl8025a 1600 2000 2400 khz f sw with rs = 402k ? 490 khz f sw with rs = 42.2k ? 4200 khz sync logic low-to-high transition range 0.70 0.75 0.80 v sync hysteresis 0.15 v sync logic input leakage current v in = 3.6v 3.6 5 a pg output low voltage 0.3 v delay time (rising edge) time from v out reached regulation 0.5 1 2 ms pg pin leakage current pg = v in 0.01 0.1 a ovp pg rising threshold 0.80 v uvp pg rising threshold 0.48 0.51 0.54 v uvp pg hysteresis 30 mv pgood delay time (falling edge) 7.5 s en logic input low 0.4 v logic input high 0.9 v en logic input leakage current pulled up to 5.5v 0.1 1 a thermal shutdown temperature rising 150 c thermal shutdown hysteres is temperature falling 25 c note: 8. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications unless otherwise noted, all parameter limits are esta blished over the recommended operating conditions and the typical specification are measured at the following conditions: t a = -40c to +85c, v in = 3.6v, en = v in , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 8) typ max (note 8) units
isl8025, isl8025a 8 fn8357.0 february 20, 2013 typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 5a. figure 4. efficiency vs load (1mhz 3.3 v in pwm) figure 5. efficiency vs load (1mhz 3.3 v in pfm) figure 6. efficiency vs load ( 1mhz 5v in pwm) figure 7. efficiency vs load ( 1mhz 5v in pfm ) figure 8. efficiency vs load ( 2mhz 3.3v in pwm) figure 9. efficiency vs load ( 2mhz 3.3v in pfm) 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) efficiency (%) 1.2v out 1.5v out 1.8v out 2.5v out 0.9v out 0.8v out 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) efficiency (%) 1.2v out 1.5v out 1.8v out 2.5v out 0.9v out 0.8v out 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) efficiency (%) 1.2v out 1.5v out 1.8v out 2.5v out 3.3v out 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) efficiency (%) 1.2v out 1.5v out 1.8v out 2.5v out 3.3v out 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) efficiency (%) 1.2v out 1.5v out 1.8v out 2.5v out 0.9v out 0.8v out 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) efficiency (%) 1.2v out 1.5v out 1.8v out 2.5v out 0.8v out 0.9v out
isl8025, isl8025a 9 fn8357.0 february 20, 2013 figure 10. efficiency vs load ( 2mhz 5v in pwm) figure 11. efficiency vs load ( 2mhz 5v in pfm) figure 12. v out regulation vs load (1mhz, v out = 0.8v) figure 13. v out regulation vs load (1mhz, v out = 0.9v) figure 14. v out regulation vs load (1mhz, v out = 1.2v) figure 15. v out regulation vs load (1mhz, v out = 1.5v) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 5a. (continued) 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) efficiency (%) 1.2v out 1.5v out 1.8v out 2.5v out 3.3v out 0.9v out 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) efficiency (%) 1.2v out 1.5v out 1.8v out 2.5v out 3.3v out 0.9v out 0.789 0.792 0.795 0.798 0.801 0.804 0.807 0.810 0.813 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) output voltage (v) 5v in pfm 5v in pwm 3.3v in pwm 3.3v in pfm 0.882 0.885 0.888 0.891 0.894 0.897 0.900 0.903 0.906 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) output voltage (v) 5v in pfm 5v in pwm 3.3v in pwm 3.3v in pfm 1.179 1.184 1.189 1.194 1.199 1.204 1.209 1.214 1.219 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) output voltage (v) 5v in pfm 5v in pwm 3.3v in pwm 3.3v in pfm 1.475 1.480 1.485 1.490 1.495 1.500 1.505 1.510 1.515 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) output voltage (v) 5v in pfm 5v in pwm 3.3v in pwm 3.3v in pfm
isl8025, isl8025a 10 fn8357.0 february 20, 2013 figure 16. v out regulation vs load (1mhz, v out = 1.8v) figure 17. v out regulation vs load (1mhz, v out = 2.5v) figure 18. v out regulation vs load (1mhz, v out = 3.3v) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 5a. (continued) 1.775 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) output voltage (v) 5v in pfm 5v in pwm 3.3v in pwm 3.3v in pfm 2.465 2.470 2.475 2.480 2.485 2.490 2.495 2.500 2.505 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) output voltage (v) 5v in pfm 5v in pwm 3.3v in pwm 3.3v in pfm 3.245 3.253 3.261 3.269 3.277 3.285 3.293 3.301 3.309 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output load (a) output voltage (v) 5v in pfm 5v in pwm
isl8025, isl8025a 11 fn8357.0 february 20, 2013 typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 5a). figure 19. start-up at no load (pfm) figure 20. start-up at no load (pwm) figure 21. shutdown at no load (pfm) figure 22. shutdown at no load (pwm) figure 23. start-up at 5a load (pwm) figure 24. shutdown at 5a load (pwm) phase 5v/div v out 1v/div 500s/div pg 5v/div v en 5v/div phase 5v/div v out 1v/div 500s/div pg 5v/div v en 5v/div phase 5v/div v out 1v/div 500s/div pg 5v/div v en 5v/div phase 5v/div v out 1v/div 500s/div pg 5v/div v en 5v/div phase 5v/div v out 1v/div pg 5v/div 500s/div v en 5v/div phase 5v/div v out 1v/div 500s/div pg 5v/div v en 5v/div
isl8025, isl8025a 12 fn8357.0 february 20, 2013 figure 25. start-up at 5a load (pfm) figure 26. shutdown at 5a load (pfm) figure 27. start-up v in at 5a load (pfm) figure 28. start-up v in at 5a load (pwm) figure 29. shutdown v in at 5a load (pfm) figure 30. shutdown v in at 5a load (pwm) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 5a). (continued) i out 2a/div v out 1v/div pg 5v/div 1ms/div v en 5v/div v en 5v/div i out 2a/div v out 1v/div pg 5v/div 200s/div v en 5v/div i out 2a/div v out 1v/div pg 5v/div 1ms/div v in 5v/div i out 2a/div v out 1v/div pg 5v/div 1ms/div v in 5v/div i out 2a/div v out 1v/div pg 5v/div 1ms/div v in 5v/div i out 2a/div v out 1v/div pg 5v/div 1ms/div v in 5v/div
isl8025, isl8025a 13 fn8357.0 february 20, 2013 figure 31. start-up v in at no load (pfm) figure 32. start-up v in at no load (pwm) figure 33. shutdown v in at no load (pfm) figure 34. shutdown v in at no load (pwm) figure 35. jitter at no load pwm figure 36. jitter at full load pwm typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 5a). (continued) phase 5v/div v out 1v/div pg 5v/div 500s/div v in 5v/div phase 5v/div v out 1v/div pg 5v/div 500s/div v in 5v/div phase 5v/div v out 1v/div v in 5v/div pg 5v/div 2ms/div phase 5v/div v out 1v/div 2ms/div v in 5v/div pg 5v/div phase 1v/div 10ns/div phase 1v/div 10ns/div
isl8025, isl8025a 14 fn8357.0 february 20, 2013 figure 37. steady state at no load pwm figure 38. steady state at no load pfm figure 39. steady state at 5a pw m figure 40. load transient (pwm) figure 41. load transient (pfm) figure 42. output short circuit typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 5a). (continued) phase 5v/div v out ripple 20mv/div il 1a/div 500ns/div phase 5v/div v out ripple 20mv/div 20ms/div il 1a/div phase 5v/div v out ripple 20mv/div 500ns/div il 2a/div v out ripple 100mv/div 200s/div il 2a/div v out ripple 100mv/div 200s/div il 2a/div phase 5v/div v out 1v/div pg 5v/div 10s/div il 2a/div
isl8025, isl8025a 15 fn8357.0 february 20, 2013 figure 43. overcurrent protection figure 44. pfm to pwm transition figure 45. pwm to pfm transition figure 46. overvoltage protection figure 47. over-temperature protection typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 5a). (continued) v out 1v/div 50s/div pg 5v/div il 5a/div phase 5v/div v out1 ripple 20mv/div 500ma mode transition, completely enter to pwm at 590ma 2s/div il 1a/div phase 5v/div v out1 ripple 20mv/div back to pfm at 420ma 2s/div il 1a/div phase 5v/div v out 1v/div 20s/div il 2a/div pg 5v/div v out 1v/div 2ms/div pg 2v/div
isl8025, isl8025a 16 fn8357.0 february 20, 2013 theory of operation the isl8025, isl8025a are step-down switching regulators optimized for battery-powered applications. the regulators operate at 1mhz or 2mhz fixed default switching frequency for high efficiency and allow smaller form factor, when fs is connected to vin. by connecting a resistor from fs to sgnd, the operational frequency adjustable range is 500khz to 4mhz. at light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. the quiescent current when the output is not loaded is typically only 50a. the supply current is typically only 5a when the regulator is shut down. pwm control scheme pulling the sync pin hi (>0.8v) forces the converter into pwm mode, regardless of output cu rrent. the isl8025, isl8025a employs the current-mode pulse-width modulation (pwm) control scheme for fast transient respon se and pulse-by-pulse current limiting. figure 3 on page 5 shows the functional block diagram. the current loop consists of the oscillator, the pwm comparator, current sensing circuit and th e slope compensation for the current loop stability. the sl ope compensation is 440mv/ts, which changes with frequency. the gain for the current sensing circuit is typically 200mv/a. the control reference for the current loops comes from the error amplifier's (eamp) output. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current amplifier csa and the slope compensation reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-fet and turn on the n-channel mosfet. the n-fet stays on until the end of the pwm cycle. figure 48 shows the typical operating waveforms during the pwm operation. the dotted lines illustrate the sum of the slope compensation ramp and the current-sense amplifier?s csa output. the output voltage is regulated by controlling the v eamp voltage to the current loop. the bandgap circuit outputs a 0.6v reference voltage to the voltage loop. the feedback signal comes from the vfb pin. the soft-start block only affects the operation during the start-up and will be discussed separately. the error amplifier is a transconductance amplifier that co nverts the voltage error signal to a current output. the voltage loop is internally compensated with the 55pf and 100k ? rc network. the maximum eamp voltage output is precisely clamped to 1.6v. skip mode pulling the sync pin lo (<0.4v) forces the converter into pfm mode. the isl8025, isl8025a ente rs a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. figure 49 illustrates the skip-mode operation. a zero-cross sensing circuit shown in figure 3 on page 5 monitors the n-fet current for zero crossing. when 16 consecutive cycles are detected, the regulator enters the skip mode. during the sixteen detecting cycles, the current in the inductor is allowed to become negative. the counter is reset to zero when the current in any cycle does not cross zero. once the skip mode is entered, the pulse modulation starts being controlled by the skip comparator shown in figure 3 on page 5. each pulse cycle is still synchronized by the pwm clock. the p-fet is turned on at the clock's rising edge and turned off when the output is higher than 1.2% of the nominal regulation or when its current reaches the peak skip current limit value. then, the inductor current is discharging to 0a and stays at zero (the internal clock is disabled), and the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p-fet will be turned on again at the rising edge of the internal clock as it repeats the previous operations. the regulator resumes normal pwm mode operation when the output voltage drops 2.5% (1.2% for 2mhz) below the nominal voltage. figure 48. pwm operation waveforms v eamp v csa duty cycle i l v out
isl8025, isl8025a 17 fn8357.0 february 20, 2013 frequency adjust the frequency of operation is fixed at 1mhz when fs is tied to vin. adjustable frequency ranges from 500khz to 4mhz via a simple resistor connecting fs to sgnd, according to equation 2: overcurrent protection the overcurrent protection is realized by monitoring the csa output with the ocp comparator, as shown in figure 3. the current sensing circuit has a gain of 200mv/a, from the p-fet current to the csa output. when the csa output reaches the threshold, the ocp comparator is trippled to turn off the p-fet immediately. the overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper mosfet. upon detection of an overcurren t condition, the upper mosfet will be immediately turned off an d will not be turned on again until the next switching cycle. upon detection of the initial overcurrent condition, the overcurren t fault counter is set to 1. if, on the subsequent cycle, another overcurrent condition is detected, the oc fault counter will be incremented. if there are 17 sequential oc fault detections, the regulator will be shut down under an overcurrent fault condition. an overcurrent fault condition will result in the regulator attempting to restart in a hiccup mode within the delay of eight soft-start periods. at the end of the 8 th soft-start wait period, the fault counters are reset and soft-start is attempted agai n. if the overcurrent condition goes away during the delay of 8 soft-start periods, the output will resume back into regulation point after hiccup mode expires. negative current protection similar to overcurrent, the negative current protection is realized by monitoring the current across the low-side n-fet, as shown in figure 3 on page 5. when the valley point of the inductor current reaches -3a for 4 consecutive cycles , both p-fet and n-fet are off. the 100 ? in parallel to the n-fet will activate discharging the output into regulation. the control will begin to switch when output is within regulation. the regulator will be in pfm for 20s before switching to pwm if necessary. pg pg is an open-drain output of a window comparator that continuously monitors the buck re gulator output voltage. pg is actively held low when en is low and during the buck regulator soft-start period. after 1ms dela y of the soft-start period, pg becomes high impedance as long as the output voltage is within nominal regulation voltage set by vfb. when vfb drops 15% below or raises 0.8v above the nominal regulation voltage, the isl8025, isl8025a pulls pg low. any fault co ndition forces pg low until the fault condition is cleared by attempts to soft-start. for logic level output voltages, connect an external pull-up resistor, r 1 , between pg and vin. a 100k resistor works well in most applications. uvlo when the input voltage is below th e undervoltage lock-out (uvlo) threshold, the regulator is disabled. soft start-up the soft-start-up reduces the in-rush current during the start-up. the soft-start block outputs a ramp reference to the input of the error amplifier. this voltage ramp limits the inductor current as well as the output voltage speed, so that the output voltage rises in a controlled fashion. when vfb is less than 0.1v at the beginning of the soft-start, the sw itching frequency is reduced to 200khz, so that the output can start-up smoothly at light load condition. during soft-start, the ic operates in the skip mode to support pre-biased output condition. tie ss to sgnd for internal soft-start is approximately 1ms. connect a capacitor from ss to sgnd to adjust the soft-start time. this capacitor, along wi th an internal 1.85a current source sets the soft-start interval of the converter, t ss , as shown by equation 3. c ss must be less than 33nf to insure proper soft-start reset after fault condition. enable the enable (en) input allows the user to control the turning on or off of the regulator for purposes, such as power-up sequencing. when the regulator is enabled, there is typically a 600s delay figure 49. skip mode operation waveforms clock i l v out nominal +1% nominal pfm current limit 0 16 cycles pwm pfm nominal -1.5% pwm load current r fs k [] 220 10 3 ? f osc khz [] ------------------------------ 14 ? = (eq. 2) c ss f [] 3.1 t ss s [] ? = (eq. 3)
isl8025, isl8025a 18 fn8357.0 february 20, 2013 for waking up the bandgap reference and then the soft-start-up begins. discharge mode (soft-stop) when a transition to shutdown mode occurs or the vin uvlo is set, the outputs discharge to gnd through an internal 100 ? switch. power mosfets the power mosfets are optimized for best efficiency. the on-resistance for the p-fet is typically 45m ? and the on-resistance for the n-fet is typically 19m ? . 100% duty cycle the isl8025, isl8025a features a 100% duty cycle operation to maximize the battery life. when the battery voltage drops to a level that the isl8025, isl8025a can no longer maintain the regulation at the output, the regulator completely turns on the p-fet. the maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the on-resistance of the p-fet. thermal shut-down the isl8025, isl8025a has built-in thermal protection. when the internal temperature reaches +150c, the regulator is completely shut down. as the temperature drops to +125c, the isl8025, isl8025a resumes operation by stepping through the soft-start. application information output inductor and capacitor selection to consider steady state and transient operations, the isl8025 typically uses a 1.0h output inductor and the isl8025a uses a 0.47f. the higher or lower inductor value can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. it is recommended to set the ripple inductor current approximately 30% of the maximum output current for optimized performance. the inductor ripple current can be expressed, as shown in equation 4: the inductor?s saturation current rating needs to be at least larger than the peak current. the isl8025, isl8025a protects the typical peak current 6a. the saturation current needs to be over 7a for maximum output current application. the isl8025, isl8025a uses an in ternal compensation network and the output capacitor value is dependent on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. the recommended x5r or x7r minimum output capacitor values are shown in table 2. in table 2, the minimum output capacitor value is given for the different output voltage to make sure that the whole converter system is stable. additional output capacitance should be added for better performances in applications where high load transient or low output ripple is required. it is recommended to check the system level performance along with the simulation model. output voltage selection the output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage, relative to the internal reference voltage, and feed it back to the inverting input of the error amplifier (refer to figure 1). the output voltage programming resistor, r 2 , will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. the value for the feedback resistor, r 3 , is typically between 10k ? and 100k ? , as shown in equation 5. if the output voltage desired is 0.6v, then r 3 is left unpopulated and r 2 is shorted. there is a leakage current from v in to phase. it is recommended to preload the output with 10a minimum. for better performance, add 15pf in parallel with r 2 (200k ? ). check loop analysis before use in application. input capacitor selection the main functions for the input capacitor are to provide decoupling of the parasitic induct ance and to provide a filtering function to prevent the switching current flowing back to the battery rail. at least two 22f x5r or x7r ceramic capacitors are a good starting point for th e input capacitor selection. loop compensation design when comp is not connected to vdd, the comp pin is active for external loop compensation. the isl8025, isl8025a uses constant frequency peak current mode control architecture to achieve a fast loop transient response. an accurate current sensing pilot device in parallel with the upper mosfet is used for peak current control signal an d overcurrent protection. the inductor is not considered as a state variable since its peak current is constant, and the system becomes a single order system. it is much easier to design a type ii compensator to stabilize the loop than to implem ent voltage mode control. peak current mode control has an inherent input voltage feed-forward function to achieve good line regulation. figure 50 shows the small signal model of the synchronous buck regulator. i v o 1 v o v in --------- ? ?? ?? ?? ? lf s ? -------------------------------------- - = (eq. 4) r 2 r 3 v o vfb ------------ 1 ? ?? ?? = (eq. 5) d v in d i l in in i l + 1:d + l i co rc -av(s) d comp v r t fm he(s) + t i (s) k o v t v (s) i l p + 1:d + rc ro -av(s) r t fm he(s) t i (s) k o t(s) ^ ^ v ^ ^ ^ ^ ^ ^ figure 50. small signal mo del of synchronous buck regulator r lp gain (vloop (s(fi))
isl8025, isl8025a 19 fn8357.0 february 20, 2013 figure 51 shows the type ii compensator and its transfer function is expressed, as shown in equation 6: where , compensator design goal: high dc gain choose loop bandwidth f c less than 100khz gain margin: >10db phase margin: >40 the compensator design procedure is as follows: the loop gain at crossover frequency of f c has a unity gain. therefore, the compensator resistance r 6 is determined by equation 7. where gm is the sum of the trans-conductance, g m , of the voltage error amplifier in each phase. compensator capacitor c 6 is then given by equation 8. put one compensator pole at zero frequency to achieve high dc gain, and put another compensator pole at either esr zero frequency or half switching frequency, whichever is lower in equation 8. an optional zero can boost the phase margin. cz2 is a zero due to r 2 and c 3 . put compensator zero 2 to 5 times f c example: v in = 5v, v o = 1.8v, i o = 4a, fs = 1mhz, r 2 = 200k , r 3 = 100k , c o = 2x22f/3m ? , l = 1h, f c = 100khz, then compensator resistance r 6 : it is acceptable to use 137k as the closest standard value for r 6 . it is also acceptable to use the closest standard values for c 6 and c 7 . there is approximately 3pf parasitic capacitance from v comp to gnd; therefore, c 7 is optional. use c 6 = 150pf and c 7 = open. use c 3 = 15pf. note that c 3 may increase the loop bandwidth from previous estimated value. figure 52 shows the simulated voltage loop gain. it is shown that it has a 150khz loop bandwidth with a 42 phase margin and 10db gain margin. it may be more desirable to achieve an increased phase margin. this can be accomplished by lowering r 6 by 20% to 30%. - + r6 v ref v fb vo gm v comp c7 - + c6 v ref v fb vo v comp figure 51. type ii compensator c3 r2 r3 a v s () v ? comp v ? fb ---------------- - gm r 3 ? c 6 c 7 + () r 2 r 3 + () ? -------------------------------------------------------- 1 s cz1 ------------ - + ?? ?? 1 s cz2 ------------ - + ?? ?? s1 s cp1 ------------- + ?? ?? 1 s cp2 ------------- + ?? ?? -------------------------------------------------------------- - = = (eq. 6 cz1 1 r 6 c 6 -------------- - cz2 1 r 2 c 3 -------------- - = cp1 , c 6 c 7 + r 6 c 6 c 7 ---------------------- - cp2 r 2 r 3 + c 3 r 2 r 3 ---------------------- - = , = , = r 6 2 f c v o c o r t gm v fb ? --------------------------------- - 17.45 3 10 f c v o c o ? == (eq. 7) c 6 r o c o r 6 -------------- - v o c o i o r 6 -------------- - c 7 max r c c o r 6 -------------- - 1 f s r 6 --------------- - (, ) = , = = (eq. 8) c 3 1 f c r 2 --------------- - = (eq. 9) r 6 17.45 3 10 100khz 1.8v 44 f ? ? ? 138k == (eq. 10) c 6 1.8v 44 ? f 4a 137k ? ------------------------------- - 144pf = = (eq. 11) c 7 max 3m 44 f ? 137k -------------------------------- - 1 1mhz 137k () ? ------------------------------------------------ (, ) 1pf 2.3pf (, ) = = (eq. 12) c 3 1 100khz 200k ? ------------------------------------------------ = 16pf = (eq. 13) figure 52. simulated loop gain 60 45 30 15 0 -15 -30 100 1k 10k 100k 1m frequency (hz) 180 150 120 90 60 30 0 100 1k 10k 100k 1m frequency (hz) phase ( ) gain (db)
isl8025, isl8025a 20 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8357.0 february 20, 2013 for additional products, see www.intersil.com/en/products.html pcb layout recommendation the pcb layout is a very important converter design step to make sure the designed converter works well. for isl8025, isl8025a, the power loop is composed of the output inductor l?s, the output capacitor (cout), the phase pins, and the pgnd pin. it is necessary to make the power loop as small as possible and the connecting traces among them shou ld be direct, short and wide. the switching node of the conv erter, the phase pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. the input capacitor should be placed as close as po ssible to the vin pin. the ground of input and output capacitors should be connected as close as possible. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for better emi performance. it is recommended to add at least 5 vias ground connection within the pad for the best thermal relief. about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the fastest growing markets wi thin the industrial and infrastructure, personal computing and high-end consumer markets. for more inform ation about intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com . for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: isl8025, isl8025a to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change february 20, 2013 fn8357.0 initial release
isl8025, isl8025a 21 fn8357.0 february 20, 2013 package outline drawing l16.3x3d 16 lead thin quad flat no-lead plastic package rev 0, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.25mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.15 index area pin 1 a 3.00 b 3.00 pin #1 b 0.10 m a c 4 6 6 0.05 1 12 4 9 13 16 8 5 1.60 sq 16x 0.23 16x 0.400.10 4x 1.50 12x 0.50 (16x 0.60) ( 1.60) (2.80 typ) (16x 0.23) (12x 0.50) c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 0.75 0.05 0.08 0.10 c c c index area see detail ?x? jedec reference draw ing: mo-220 weed. 7.

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